DMA controllers are used in known computer systems for offloading, from a CPU, the tasks of performing data transfers to and from memory. If the CPU itself were used to transfer, for example, each byte of a program stored on an external floppy disk into the system memory for execution, operations would be severely slowed and overall system performance severely degraded. A DMA controller can instead be used to load the program, freeing the CPU for other operations.
Typically, the CPU gives the DMA controller a start address and a byte count for data to be transferred to or from the memory. The DMA controller then proceeds to perform the data transfer.
Among disadvantages of known systems, however, is that events that may occur during transfers of data by the DMA controller are not adequately monitored or signaled. In known systems, for example, only the start and the completion of a data transfer are signaled. The completion event may be signaled, for example, by generating an interrupt or by setting a status bit in a register that is polled by the CPU.
However, other events that impact system availability may occur during DMA data transfers, and need to be tracked. One example of such an event is a data transfer being aborted. An abort signal may be generated by a peripheral device to which a DMA transfer has begun, to signal that the DMA transfer has been stopped short of successful completion. The peripheral device might abort a DMA transfer, for example, because of a software or hardware failure. In conventional systems, such an abort signal may be treated as equivalent to a completion signal indicating a successful transfer of data. Thus, information which could be useful in identifying failing devices or system failures may be lost.
Another example of such an event is a DMA transfer which is begun but never completed (either successfully or unsuccessfully). A DMA controller might, for instance, set a status bit indicating that data transfer to a peripheral device had begun, but the peripheral device might not be ready to receive the data, or might have failed during the data transfer. The DMA controller might, in such a situation, continually attempt to send data to the device, but unsuccessfully because the device is not ready or has failed. The status bit would continue to indicate that a data transfer was underway, while in fact no data transfer was occurring. This would waste DMA resources, since the DMA channel attempting to send the data could be used for other data transfers.
A mechanism that generates a “timeout” is known for handling such situations. A timeout is a signal, typically an interrupt, generated when an operation does not complete in a time allotted for it. Conventional DMA controllers typically do not generate timeouts for stalled or incomplete data transfers as described above.
Additionally, DMA transfers may suffer from “unfair” bus arbitration. That is, a peripheral device that needs to transfer data to or from the memory may be connected to a bus shared with other devices, but access to the bus for the DMA controller, for purposes of effecting the data transfer, may be inadequate or unduly delayed.
A method and system are needed that address the foregoing concerns.